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#ifndef __HTREE2_H__
#define __HTREE2_H__

#include "assert.h"
#include "basic_circuit.h"
#include "cacti_interface.h"
#include "component.h"
#include "parameter.h"
#include "subarray.h"
#include "wire.h"

namespace cacti {

// leakge power includes entire htree in a bank (when uca_tree == false)
// leakge power includes only part to one bank when uca_tree == true

class Htree2 : public Component {
 public:
  Htree2(enum Wire_type wire_model, double mat_w, double mat_h, int add,
         int data_in, int search_data_in, int data_out, int search_data_out,
         int bl, int wl, enum Htree_type h_type, bool uca_tree_ = false,
         bool search_tree_ = false,
         TechnologyParameter::DeviceType *dt = &(g_tp.peri_global));
  ~Htree2(){};

  void in_htree();
  void out_htree();

  // repeaters only at h-tree nodes
  void limited_in_htree();
  void limited_out_htree();
  void input_nand(double s1, double s2, double l);
  void output_buffer(double s1, double s2, double l);

  double in_rise_time, out_rise_time;

  void set_in_rise_time(double rt) { in_rise_time = rt; }

  double max_unpipelined_link_delay;
  powerDef power_bit;

 private:
  double wire_bw;
  double init_wire_bw;  // bus width at root
  enum Htree_type tree_type;
  double htree_hnodes;
  double htree_vnodes;
  double mat_width;
  double mat_height;
  int add_bits, data_in_bits, search_data_in_bits, data_out_bits,
      search_data_out_bits;
  int ndbl, ndwl;
  bool uca_tree;  // should have full bandwidth to access all banks in the array
                  // simultaneously
  bool search_tree;

  enum Wire_type wt;
  double min_w_nmos;
  double min_w_pmos;

  TechnologyParameter::DeviceType *deviceType;
};

}  // namespace cacti

#endif
